1. Field of the Invention
The present invention relates to a PDP (plasma display panel) driving method and device.
2. Description of the Related Art
Recently, LCDs (liquid crystal displays), FEDs (field emission displays), and PDPs have been actively developed. PDPs have wider view angles and better luminance and light emission efficiency than other types of flat panel devices. Therefore, PDPs have come into the spotlight as substitutes for the conventional CRTs (cathode ray tubes) for large displays of greater than 40 inches.
A PDP is a flat display that uses plasma, which is generated via a gas discharge process, to display characters or images, and tens to millions of pixels are provided thereon in a matrix format, depending on its size. PDPs are categorized into DC PDPs and AC PDPs, according to the supplied driving voltage waveforms and discharge cell structures.
Since DC PDPs have electrodes that are exposed in the discharge space, DC PDPs allow the current to flow in the discharge space while the voltage is supplied, and therefore they problematically require resistors for current restriction. On the other hand, since AC PDPs have electrodes that are covered by a dielectric layer, capacitances are naturally formed to restrict the current, and the electrodes are protected from ion shocks in the case of discharging. Accordingly, AC PDPs have a longer lifespan than DC PDPs.
As shown in FIG. 1, in an AC PDP a scan electrode 4 and a sustain electrode 5, which are disposed over a dielectric layer 2 and a protection film 3, are provided in parallel and form a pair with each other under a first glass substrate 1. A plurality of address electrodes 8 covered with an insulation layer 7 are installed on a second glass substrate 6. Barrier ribs 9 are formed on the insulation layer 7 between the address electrodes 8. The barrier ribs are parallel with the address electrodes 8, and phosphor 10 is formed on the surface of the insulation layer 7 between the barrier ribs 9. The first glass substrate 1 and the second glass substrate 6 have a discharge space 11 between them and face each other so that the scan electrode 4 and the sustain electrode 5 may respectively cross the address electrode 8. The address electrode 8 and a discharge space 11 formed at a crossing part of the scan electrode 4 and the sustain electrode 5 form a discharge cell 12.
As shown in FIG. 2, the PDP electrode has an m×n matrix configuration. The PDP electrode, it has address electrodes A1 to Am in the column direction, and scan electrodes Y1 to Yn and sustain electrodes X1 to Xn in the row direction, alternately. The discharge cell 12 shown in FIG. 2 corresponds to the discharge cell 12 shown in FIG. 1.
In general, a method for driving the AC PDP includes a reset period, an addressing period, and a sustain period.
In the reset period, the states of the respective cells are reset in order to smoothly address the cells. In the addressing period, the cells that are turned on and the cells that are not turned on in a panel are selected, and wall charges are accumulated to the cells that are turned on (i.e., the addressed cells). In the sustain period, discharge is performed in order to actually display pictures on the addressed cells.
An important part for designing waveforms for driving the PDP is a reset waveform. A reset waveform of conventional AC PDPs and a corresponding driving method will now be described.
The reset period erases the majority, and preferably all, of the wall charges formed by a previous discharge, and sets up the wall charges to fluently perform a next address discharge. The PDP has millions of cells, each of which has a slightly different discharge voltage. However, a respective cells' discharges are controlled using a single predetermined voltage, thereby causing many difficulties. In the reset period, it is very important to erase and reset the wall charges and to solve the difference of discharge voltage provided between the cells. The reset waveform includes a part for erasing the wall charges generated by a previous discharge, and a process for rearranging the wall charges to solve discharge voltage dispersion between the cells and easily perform addressing.
That is, the reset period represents a period for supplying a voltage in a predetermined format to easily perform an operation of a subsequent addressing period. A PDP with bad uniformity between the cells may stably display images according to an operation characteristic during this period.
The waveforms generally used for stable operation of a display with low uniformity between cells during the current reset period is a ramp waveform disclosed, for example, by U.S. Pat. No. 5,745,086 and shown in FIG. 3. The gentler the slope of the ramp waveform, the more stable a display with low uniformity between the cells is operated. The slope should be substantially below 15 V/us, and for stable operation, it is preferable to have a slope of about 1 to 2 V/us. When, for example, the voltage is 400V(volts), for a slope of about 1 V/us, twice 200 us, that is, 400 us is required, which is too much time. Accordingly, the waveform illustrated in FIG. 4, which is an improvement of the above waveform, is generally used. Referring to FIG. 4, the waveform is not formed into a ramp waveform until it has reached a desired voltage. The voltage is instantly modified by as much of a voltage that may not generate discharging in the discharge cells of the PDP is instantly modified, and a ramp waveform is applied after this.
A prior art PDP driver comprises a sustain waveform former and a ramp waveform former. The sustain waveform former includes switches for applying waveforms in the sustain period, and each switch is an element having a large capacity for storing a large current used during the sustain period and each is driven at a low voltage.
However, the ramp waveform former uses the high voltages that are used for the reset period, and includes a main path switch for cutting the ramp waveform former and the sustain waveform former. By cutting the ramp waveform former and the sustain waveform former, it is possible to thereby prevent the high voltage used for the reset period from being supplied to a large-capacity element for applying the waveforms of the sustain period, and it enables the use of cheap elements.
Rising and falling ramp switches of the ramp waveform former connect a capacitor positioned between a drain electrode and a gate electrode of an FET so as to apply a ramp waveform. A ramp waveform is, a gradually increasing or decreasing voltage waveform. Since a constant voltage flows between the drain and the gate because of the capacitor, a constant current flows between the drain and the gate. Accordingly, a voltage having a ramp waveform is supplied to a panel capacitor.
However, the PDP driving circuit separately uses a main path switch for preventing a high voltage for supplying a reset waveform from being supplied to a circuit for supplying sustain waveforms, and a falling ramp switch for supplying falling ramp waveforms to scan electrodes. The above-noted driving circuit with separate switches is not efficient when considering that the switches are expensive.